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Iiit Processor Instruction Set

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Instruction Set Sl.No. Instruction 1 nop 2 stop 3 adi xx 4 subi xx 5 xri xx 6 ani xx 7 ori xx 8 cmi xx 9ret 16 17 add 18 sub 19 xor 20 and 21 or 22 cmp 23 movs 24 movd 25 movi xx 26 store 27 load 28 push 29 pop 30jmpd xx 37 38jmpr 45

for the Single-Bus Processor Architecture Action Op Code (Hex) No action 00 Exit the program 01 02 [AR] ← [AR] + xx 03 [AR] ← [AR] – xx 04 [AR] ← [AR] ⊕ xx 05 [AR] ← [AR] ∧ xx 06 [AR] ← [AR] ∨ xx [AR] – xx (Flags only) 07 [PC] ← [[SP]], [SP] ← [SP]+1 08 to 0F if = 1 10-1F (n:0-F) [AR] ← [AR] + [] 20-2F (n:0-F) [AR] ← [AR] – [] 30-3F(n:0-F) [AR] ← [AR] ⊕ [] 40-4F(n:0-F) [AR] ← [AR] ∧ [] 50-5F(n:0-F) [AR] ← [AR] ∨ [] [AR] – [] (Flags only) 60-6F(n:0-F) 70-7F(n:0-F) [OR] ← [], [AR] ← [] 80-8F(n:0-F) [] ← [AR] 90-9F(n:0-F) [] ← xx [[AR]] ← [] [] ← [[AR]] [SP] ← [SP]–1, [[SP]] ← [] [] ← [[SP]], [SP] ← [SP]+1 [PC] ← xx if = 1 [PC] ← [AR] if = 1 A0-AF(n:0-F) B0-BF(n:0-F) C0-CF(n:0-F) D0-DF(n:0-F) E0 to E7 E8 to EF

46[SP] ← [SP]–1, [[SP]]← [PC], cd xx F0 to F7 53 [PC] ← xx if = 1 54[SP] ← [SP]–1, [[SP]]← PC], cr F8 to FF 61 [PC] ← [AR] if = 1 Flags: Zero (Z), Carry (CY), Sign (S), Parity (P) = u/z/nz/c/nc/p/m/op ⇒ FL = 0/Z/Z’/CY/CY’/S/S’/1 if Parity odd = r1/r2/r3/r4/r5/r6/r7/r8/r9/r10/r11/PC/SP/AR/OR ALU Function Codes: 0000 0001 0010 0011 0100 0101 0110 1111 ADD SUB XOR AND OR CMP A1

Architecture based on a Single Internal Data Bus
RD WR Address Bus LMR Memory Address Register (MR)

Memory and Input/Output Ports
SRG Data Bus Operand Register (OR) EOR ROR LOR A1 Program Counter (PC) SRG A2 SAF



Stack Pointer (SP)

Accumulator (AR)



Instruction Register (IR) Decoder Microprogram Address (SA)

Register Array (RG) SRG Register/Flag Selection Bits from Op Code SFL Selected Flag Flag Register



Microprogram Sequencer (MS)…...

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