Free Essay

Differential Manchester Encoding

In: Computers and Technology

Submitted By owallis1
Words 429
Pages 2

1. Rules

The Differential Manchester encoding rules (after Halsall) are as follows:

1. There is a transition at the start of the bit if the data is a logic ‘0’
Note: Tanenbaum has a transition for a logic ‘1’ instead.

2. There is always a transition in the middle of the bit.

3. The direction of the transition is immaterial (hence there are two possible waveforms for any data stream depending upon the initial conditions).

This gives us the following sample test data assuming pairs of logic levels for one actual bit:

Data 1 1 0 0 1 0 1 1

Differential 01 10 10 10 01 01 10 01
Manchester (1)

Differential 10 01 01 01 10 10 01 10
Manchester (2)

After Halsall

2. Design Steps

The output is toggling which suggests a flip flop.

If Data = ‘0’ Output = Clock or inverse clock

If Data = ‘1’ Output = 2 on –ve clock or inverse 2 on –ve clock

Hence the output must be made up of two AND gates and an OR gate to select either * clock or inverse clock when Data = ‘0’ or * 2 on –ve clock or inverse 2 on –ve clock if Data = ‘1’

By De Morgan’s theorem (A.B)+(C.D) = (A.B).(C.D)

So we can use three 2 input NAND gates instead of two 2 input AND gates and one 2 input OR gate.

Finally we need to flesh out the additional circuitry required.

3. Test Data set

The actual test data needs to be more along the following lines:

Data 0 0 0 0 0 0 0

Output 10 10 10 10 10 10 10 01 01 01 01 01 01 01

Data 1 1 1 1 1 1 1

Output 01 10 01 10 01 10 01 10 01 10 01 10 01 10

Data 0 1 0 1 0 1 0

Output 10 01 01 10 10 01 01 01 10 10 01 01 10 10

4. Circuit

Check the following circuit to see if it meets the requirements of 3. above?

The two buffers with inverted signal inputs are “tri-state buffers”. When the input signal from the D type flip flop is a “1” then the output is high impedance. When the input signal from the D type flip flop is a “0” then the output is a buffered version of whatever is on the normal signal input.

The three output gates can be reduced to NAND gates using De Morgan’s theorem. You might wish to check this in MultiSim or PSpice.…...

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